Generally, a transistor is formed using an active region isolated by a device isolation layer in a semiconductor substrate. The transistor may have a planar-type gate pattern on the active region, and source/drain regions in the semiconductor substrate that underlie the planar-type gate pattern. A channel region is disposed in the semiconductor substrate under the planar-type gate pattern. The channel region allows charges in the semiconductor substrate to flow into the source region, or into the drain region.
With a design rule of semiconductor devices scaled down, sizes of the channel region, the planar-type gate pattern and the source/drain regions of the transistor are also reduced. In order to cope with the above scaling-down, there may be introduced, a trench-shaped channel-portion hole in the semiconductor substrate and a gate pattern filling the channel-portion hole instead of the planar-type gate pattern. At this time, the gate pattern filling the channel-portion hole has a channel region in the semiconductor substrate confining the channel-portion hole. The channel region around the gate pattern filling the channel-portion hole has a dimension greater than that under the planar-type gate pattern.
However, the semiconductor device having the channel-portion hole may have a device isolation layer that is disposed at a lower level than an upper surface of the active region of the semiconductor substrate. The channel-portion hole may be formed by performing an etch process in the semiconductor substrate, using self-aligned patterns on the semiconductor substrate as an etch mask. At this time, the etch process may remove a portion of the device isolation layer, thereby deteriorating electrical characteristics of the transistor.
U.S. Pat. No. 6,069,091 to Fa-Yuan Chang, et. al. discloses in-situ sequential silicon containing hard mask layer/ silicon layer plasma etch method. According to the '091 patent, the method includes providing a semiconductor substrate, and sequentially forming a blanket silicon layer and a blanket silicon-containing hard mask layer on the semiconductor substrate. Further, a patterned photoresist layer is formed on the blanket silicon-containing hard mask layer. The blanket silicon-containing hard mask layer is formed of one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a composite of the above materials. The blanket silicon layer is formed of silicon.
The method includes performing a first plasma etch process on the blanket silicon-containing hard mask layer, using the patterned photoresist layer as an etch mask. The first plasma etch process forms a patterned silicon-containing hard mask layer on the blanket silicon layer. The first plasma etch process may be performed using a bromine-containing etchant source gas along with an etchant source gas containing fluoride and carbon. The method further includes performing a second plasma etch process on the blanket silicon layer, using the patterned photoresist layer and the patterned silicon-containing hard mask layer. The second plasma etch process forms at least a partially etched silicon layer on the semiconductor substrate. At this time, the second plasma etch process may be performed using a chlorine-containing enchant source gas together with an etchant source gas containing fluoride and carbon, and a bromine-containing etchant source gas.
Unfortunately, the method includes generating byproducts of SixFy, SixBry and SixCly using the etchant source gases of the second plasma etch process at a point of exposing the semiconductor substrate. These by-products are volatile gases and may etch the semiconductor substrate. Further, in the case that the second plasma etch process is performed on the semiconductor substrate having a device isolation layer, the device isolation layer can be removed. As a result, electrical characteristics of a transistor may be deteriorated.